| Presentation | 2010-11-30 FPGA design and test methodology for communication frame processing Ritsu KUSABA, Kenji KAWAI, Sadayuki YASUDA, Satoshi SHIGEMATSU, Mamoru NAKANISHI, Masami URANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For large-scale and high-speed frame processing on a FPGA board, we propose a new design method based on the property of communication frame processing. To prevent increases in the design period, we also propose a test method that uses substitutional and loop-backed circuits. The board communicates with terminals emulating the FEC (Forward Error Correction) or encryption format. We have finished the logical design of an evaluation board with seven F PGAs and verified that communication frames are transmitted and received before the block design is completed . |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / design / communication frame / test |
| Paper # | VLD2010-67,DC2010-34 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA design and test methodology for communication frame processing |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | design |
| Keyword(3) | communication frame |
| Keyword(4) | test |
| 1st Author's Name | Ritsu KUSABA |
| 1st Author's Affiliation | NTT Microsystem Integration Laboratories() |
| 2nd Author's Name | Kenji KAWAI |
| 2nd Author's Affiliation | NTT Microsystem Integration Laboratories |
| 3rd Author's Name | Sadayuki YASUDA |
| 3rd Author's Affiliation | NTT Microsystem Integration Laboratories |
| 4th Author's Name | Satoshi SHIGEMATSU |
| 4th Author's Affiliation | NTT Microsystem Integration Laboratories |
| 5th Author's Name | Mamoru NAKANISHI |
| 5th Author's Affiliation | NTT Microsystem Integration Laboratories |
| 6th Author's Name | Masami URANO |
| 6th Author's Affiliation | NTT Microsystem Integration Laboratories |
| Date | 2010-11-30 |
| Paper # | VLD2010-67,DC2010-34 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |