Presentation 2010-11-30
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes
Satoshi TAKEYASU, Masashi IMAI, Hiroshi NAKAMURA,
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Abstract(in English) GALS-NoC is recently paid attention. Beside, NoC have commonly bias of packets transfer routes by regularity of network topology and routing algorithm. By focusing on the bias, we propose high performance and area efficient asynchronous NoC. the NoC(2D-mesh, xy-routing) is designed with a 65nm CMOS process and evaluated in terms of the area and peak-throughput, the proposed method can increase the peak- throughput by 2.8% and the area by 6.7%.
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Keyword(in English) asynchronous / GALS / NoC / bias
Paper # VLD2010-66,DC2010-33
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Committee DC
Conference Date 2010/11/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes
Sub Title (in English)
Keyword(1) asynchronous
Keyword(2) GALS
Keyword(3) NoC
Keyword(4) bias
1st Author's Name Satoshi TAKEYASU
1st Author's Affiliation Graduate school of information Science and Technology, The University of Tokyo()
2nd Author's Name Masashi IMAI
2nd Author's Affiliation Komaba Open Laboratory, The University of Tokyo
3rd Author's Name Hiroshi NAKAMURA
3rd Author's Affiliation Graduate school of information Science and Technology, The University of Tokyo
Date 2010-11-30
Paper # VLD2010-66,DC2010-33
Volume (vol) vol.110
Number (no) 317
Page pp.pp.-
#Pages 6
Date of Issue