Presentation 2010-11-30
Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors
Ittetsu TANIGUCHI, Mitsuya UCHIDA, Hiroyuki TOMIYAMA, Masahiro FUKUI,
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Abstract(in English) Reducing energy consumption is a crucial for the embedded system design, and especially, the leakage energy reduction is now big problem for the low power design. In order to reduce the leakage energy at standby time, power gating scheme is well known as a promising technique to realize partial power shutdown. However, the power gating usually causes cycle and energy penalties. In this paper, we propose energy aware instruction scheduling for fine grained power gated VLIW processors. Proposed scheduling algorithm is formulated by 0-1 ILP (integer linear programming).
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Keyword(in English) Instruction Scheduling / Low Power Design / VLIW Processors / Power Gating
Paper # VLD2010-65,DC2010-32
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Committee DC
Conference Date 2010/11/22(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors
Sub Title (in English)
Keyword(1) Instruction Scheduling
Keyword(2) Low Power Design
Keyword(3) VLIW Processors
Keyword(4) Power Gating
1st Author's Name Ittetsu TANIGUCHI
1st Author's Affiliation Faculty of Science and Engineering, Ritsumeikan University()
2nd Author's Name Mitsuya UCHIDA
2nd Author's Affiliation Faculty of Science and Engineering, Ritsumeikan University
3rd Author's Name Hiroyuki TOMIYAMA
3rd Author's Affiliation Faculty of Science and Engineering, Ritsumeikan University
4th Author's Name Masahiro FUKUI
4th Author's Affiliation Faculty of Science and Engineering, Ritsumeikan University
Date 2010-11-30
Paper # VLD2010-65,DC2010-32
Volume (vol) vol.110
Number (no) 317
Page pp.pp.-
#Pages 6
Date of Issue