| Presentation | 2010-11-30 Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi TAWADA, Masao YANAGISAWA, Tatsuo OHTSUKI, Nozomu TOGAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded systems, cache configuration can be optimized due to the limitation of target applications. For LRU cache replacement policy, Recently, the CRCB approach has been proposed for LRU-based cache configuration simulation, that can calculate cache hit/miss rate accurately and very fast changing the three parameters described above. However many recent processors use FIFO-based caches instead of LRU-based caches. In this paper, we propose a faster cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then we propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativity simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and an average of 18% faster than the conventional simulators. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2010-64,DC2010-31 |
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| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy |
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| 1st Author's Name | Masashi TAWADA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 3rd Author's Name | Tatsuo OHTSUKI |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2010-11-30 |
| Paper # | VLD2010-64,DC2010-31 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
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