Presentation	2010-11-29 A Scalable Heuristic for Incremental High-Level Synthesis Shohei ONO, Hiroaki YOSHIDA, Masahiro FUJITA,
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Abstract(in English)	Due to extremely high non-recurring-engineering costs in ASIC development, incremental synthesis techniques have been becoming increasingly important. Although incremental logic synthesis, placement and routing have been available for a while, incremental high-level synthesis is still a challenging problem. In this paper, we propose a practical incremental high-level synthesis method. We also evaluate the quality of the result of the proposed method by comparing with the result of the exact method.
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Keyword(in English)	incremental high-level synthesis / Engineering Change Order (ECO)
Paper #	VLD2010-59,DC2010-26
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Committee	DC
Conference Date	2010/11/22(1days)
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Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	A Scalable Heuristic for Incremental High-Level Synthesis
Sub Title (in English)
Keyword(1)	incremental high-level synthesis
Keyword(2)	Engineering Change Order (ECO)
1st Author's Name	Shohei ONO
1st Author's Affiliation	Dept. of Electrical Engg. & Information Systems, the University of Tokyo()
2nd Author's Name	Hiroaki YOSHIDA
2nd Author's Affiliation	VLSI Design and Education Center (VDEC):CREST, Japan Science and Technology Agency
3rd Author's Name	Masahiro FUJITA
3rd Author's Affiliation	VLSI Design and Education Center (VDEC):CREST, Japan Science and Technology Agency
Date	2010-11-29
Paper #	VLD2010-59,DC2010-26
Volume (vol)	vol.110
Number (no)	317
Page	pp.pp.-
#Pages	6
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