Presentation | 2010-11-29 Rapid SoC Prototyping Based on Virtual Multi-Processor Model Hiroaki YOSHIDA, Masahiro FUJITA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | To meet both high performance and high energy efficiency, System-on-Chip (SoC) has a heterogenous architecture including many application-specific accelerators. As a design methodology for such heterogeneous SoCs, we propose a rapid SoC prototyping method based on virtual multi-processor model. Starting from a flexible, homogenous multi-processor model, the proposed method iteratively improves the energy efficiency by identifying inefficient portions of the design and replacing them with specialized hardware. Also, we present a SoC design environment Cyneum which we have been developing recently. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | System-on-Chip (Soc) / virtual multi-processor model / high-level synthesis / high energy effeciency |
Paper # | VLD2010-58,DC2010-25 |
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Committee | DC |
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Conference Date | 2010/11/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Rapid SoC Prototyping Based on Virtual Multi-Processor Model |
Sub Title (in English) | |
Keyword(1) | System-on-Chip (Soc) |
Keyword(2) | virtual multi-processor model |
Keyword(3) | high-level synthesis |
Keyword(4) | high energy effeciency |
1st Author's Name | Hiroaki YOSHIDA |
1st Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo:CREST, Japan Science and Technology Agency() |
2nd Author's Name | Masahiro FUJITA |
2nd Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo:CREST, Japan Science and Technology Agency |
Date | 2010-11-29 |
Paper # | VLD2010-58,DC2010-25 |
Volume (vol) | vol.110 |
Number (no) | 317 |
Page | pp.pp.- |
#Pages | 6 |
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