| 講演名 | 2010/10/21 Hardware Efficient Hybrid Logarithmic Approach For RRC filter Design in DVB-S2 Receiver , |
|---|---|
| PDFダウンロードページ | PDFダウンロードページへ |
| 抄録(和) | |
| 抄録(英) | Computational complexity of a Root Raised Cosine Filter is dominated by the binary multiplications involved in process. In this paper, a hybrid logarithmic approach has been used to design multiplier-less RRC filter to achieve optimized hardware. Hybrid-logarithmic arithmetic is advantageous for FIR digital filters since it removes the necessity for the use of high speed array multipliers. These are replaced by simple look up tables for the conversion to and from the logarithmic domain. Matlab simulations have been performed to show the performance of hybrid-logarithmic filter. It offers a significant reduction in complexity when compared to floating point equivalents proposed for the DVB-S2 receiver applications. The use of hybrid logarithmic arithmetic also has the potential to reduce the power consumption, latency and hardware complexity. The given approach can be used with other DVB-S2 receiver techniques like symbol timing synchronization, carrier offset estimation etc. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving over the conventional binary multiplier approach. The functionality of the design has been verified through simulation and synthesis of the existing and proposed RRC filter scheme. |
| キーワード(和) | |
| キーワード(英) | Digital Video Broadcasting second Generation / Root Raised Cosine Filter / Logarithmic Number System / Matched Filter |
| 資料番号 | SAT2010-53 |
| 発行日 |
| 研究会情報 | |
| 研究会 | SAT |
|---|---|
| 開催期間 | 2010/10/21(から1日開催) |
| 開催地（和） | |
| 開催地（英） | |
| テーマ（和） | |
| テーマ（英） | |
| 委員長氏名（和） | |
| 委員長氏名（英） | |
| 副委員長氏名（和） | |
| 副委員長氏名（英） | |
| 幹事氏名（和） | |
| 幹事氏名（英） | |
| 幹事補佐氏名（和） | |
| 幹事補佐氏名（英） | |
| 講演論文情報詳細 | |
| 申込み研究会 | Satellite Telecommunications (SAT) |
|---|---|
| 本文の言語 | ENG |
| タイトル（和） | |
| サブタイトル（和） | |
| タイトル（英） | Hardware Efficient Hybrid Logarithmic Approach For RRC filter Design in DVB-S2 Receiver |
| サブタイトル（和） | |
| キーワード(1)（和/英） | / Digital Video Broadcasting second Generation |
| 第 1 著者 氏名（和/英） | / Vikas Agarwal |
| 第 1 著者 所属（和/英） | Satellite & Wireless Convergence Research Department Electronics and Telecommunications Research Institute (ETRI) |
| 発表年月日 | 2010/10/21 |
| 資料番号 | SAT2010-53 |
| 巻番号（vol） | vol.110 |
| 号番号（no） | 256 |
| ページ範囲 | pp.- |
| ページ数 | 5 |
| 発行日 | |