Presentation | 2010-09-17 Implementaton and evaluation of ScalableCore system 2.0 Yoshito SAKAGUCHI, Shinya TAKAMAEDA, Kenji KISE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | ScalableCore is a concept of prototyping system development by using a lot of FPGAs for Many-core architecture researches. In this paper, we present a new FPGA platform named ScalableCore system 2.0. This system realizes higher speed FPGA-FPGA communications than previous platform, ScalableCore System Version 1. We discussed the timing model of the system from basis of the observed communications speed. According to the timing model, we also estimate the simulation speed. To simulate a processor of 64 nodes, ScalableCore 2.0 is about 64 times faster than the software simulator; SimMc. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / Many-core processor / evaluation environment / prototyping |
Paper # | RECONF2010-38 |
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Committee | RECONF |
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Conference Date | 2010/9/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Implementaton and evaluation of ScalableCore system 2.0 |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | Many-core processor |
Keyword(3) | evaluation environment |
Keyword(4) | prototyping |
1st Author's Name | Yoshito SAKAGUCHI |
1st Author's Affiliation | Tokyo Institute of Technology() |
2nd Author's Name | Shinya TAKAMAEDA |
2nd Author's Affiliation | Tokyo Institute of Technology |
3rd Author's Name | Kenji KISE |
3rd Author's Affiliation | Tokyo Institute of Technology |
Date | 2010-09-17 |
Paper # | RECONF2010-38 |
Volume (vol) | vol.110 |
Number (no) | 204 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |