| Presentation | 2010-09-17 Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration Masayuki KIMURA, Kazuei HIRONAKA, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As mobile devices have many functions, these are required to be more performance and low-power computation. Dynamically Reconfigurable Processor Array(DRPA) is received an attention as a way to accomplish these requirements. Applications executed on DRPA is described by high-level programming languages such as C. Despite many compilers for DRPA developed in the past is focused on performance of execution, compiler focused to be low-power execution have not been researched. In this paper, we propose low-power orientetd mapping algorithm for DRPA compiler. Our algorithm can reduce power consumption by minimizing number of re-configuration. Start from existing mapping generated by normal compiler, our algorithm re-maps operations and operands to array of Processing Element not to be exchanged as possible. We evaluated our algorithm using prototype chip of DRPA MuCCRA-3, developed in our laboratory. Compared with normal mapping algorithm, our algorithm can reduce consuming power in 10.6%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable System / Compiler / Low Power Design |
| Paper # | RECONF2010-35 |
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| Committee | RECONF |
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| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable System |
| Keyword(2) | Compiler |
| Keyword(3) | Low Power Design |
| 1st Author's Name | Masayuki KIMURA |
| 1st Author's Affiliation | Faculty of science and Technology, Keio University() |
| 2nd Author's Name | Kazuei HIRONAKA |
| 2nd Author's Affiliation | Faculty of science and Technology, Keio University |
| 3rd Author's Name | Hideharu AMANO |
| 3rd Author's Affiliation | Faculty of science and Technology, Keio University |
| Date | 2010-09-17 |
| Paper # | RECONF2010-35 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |