| Presentation | 2010-09-17 Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota ISHIHARA, Ryoto TSUCHIYA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock tree. On the other hand, a synchronous circuit is power-efficient for high-workload sub-circuits because of its simple hardware. Exploiting the advantages of the synchronous circuit and the asynchronous circuit, each sub-circuit of the proposed FPGA performs as either synchronous circuit or asynchronous circuit according to its workload. Since the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, the major concern is designing the functional unit which is efficient for both asynchronous and synchronous circuits. In order to fully exploiting the hardware resources, in the proposed FPGA, a functional unit can be selected to perform as either a single asynchronous four-input LUT or two synchronous four-input LUTs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / reconfigurable VLSI / asynchronous architecture / four-phase dual-rail encoding |
| Paper # | RECONF2010-33 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | reconfigurable VLSI |
| Keyword(3) | asynchronous architecture |
| Keyword(4) | four-phase dual-rail encoding |
| 1st Author's Name | Shota ISHIHARA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Ryoto TSUCHIYA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Yoshiya KOMATSU |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Masanori HARIYAMA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 5th Author's Name | Michitaka KAMEYAMA |
| 5th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2010-09-17 |
| Paper # | RECONF2010-33 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |