| Presentation | 2010-09-17 An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device Qian ZHAO, Yoshihiro ICHINOMIYA, Yasuhiro OKAMOTO, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the size of integrated circuit has reached the nanoscale, embedded memories are more sensitive to single event upset (SEU), because of their low threshold voltage. In particular field-programmable gate arrays (FPGAs), which contain large amounts of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEU. In this research, we first develop a Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then employ a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input proposed architecture save about 75.44 and 74.29% memories on average, respectively. And the dependability of proposed architecture is about 10 times better than the LUT with TMR architecture on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fault tolerant / Hamming code / FPGA |
| Paper # | RECONF2010-32 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device |
| Sub Title (in English) | |
| Keyword(1) | Fault tolerant |
| Keyword(2) | Hamming code |
| Keyword(3) | FPGA |
| 1st Author's Name | Qian ZHAO |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kumamoto University() |
| 2nd Author's Name | Yoshihiro ICHINOMIYA |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 3rd Author's Name | Yasuhiro OKAMOTO |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 4th Author's Name | Motoki AMAGASAKI |
| 4th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 5th Author's Name | Masahiro IIDA |
| 5th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| 6th Author's Name | Toshinori SUEYOSHI |
| 6th Author's Affiliation | Graduate School of Science and Technology, Kumamoto University |
| Date | 2010-09-17 |
| Paper # | RECONF2010-32 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |