| Presentation | 2010-09-17 COGRE : A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro OKAMOTO, Yoshihiro ICHINOMIYA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) as programmable logic cells. N-input LUTs can implement any N-input logic functions. However, there is no need to use all logic functions in a circuit implementation. Therefore, we can cut down the area and configuration memory bits of logic cells by decreasing the functionality. In this paper, we propose a novel small-memory logic cell, c0GRE, to minimize the FPGA area. The experimental results show that the logic area in 6-COGRE is 46.3% smaller than that in 6-LUT. The logic area of 5-COGRE is 32.6% smaller than that of 5-LUT and 10.0% smaller than that of 4-LUT. Further, the total number of configuration memory bits in 6-COGRE is 32.1% smaller than the number of configuration memory bits in 6-LUT. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic device / logic cell / NPN equivalence class |
| Paper # | RECONF2010-31 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | COGRE : A Novel Compact Logic Cell Architecture for Area Reduction |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic device |
| Keyword(2) | logic cell |
| Keyword(3) | NPN equivalence class |
| 1st Author's Name | Yasuhiro OKAMOTO |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Yoshihiro ICHINOMIYA |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Motoki AMAGASAKI |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Masahiro IIDA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Toshinori SUEYOSHI |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2010-09-17 |
| Paper # | RECONF2010-31 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |