| Presentation | 2010-09-16 Design and Implementation of a GUI Tool for Circuit Design on MPLDs Ken TAOMOTO, Hideyuki KAWABATA, Masato INAGI, Kazuya TANIGAWA, Tetsu HIRONAKA, Masayuki SATO, Takashi ISHIGURO, Toshiaki KITAMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A rapidly and partially reconfigurable fine-grain programmable logic device, named MPLD, has been proposed. The MPLD architecture is organized as an array of basic elements called MLUTs. Because an MLUT can be used as a logic block or a wiring element, MPLD does not need any wiring facility, which might result higher circuit package density of MPLD chips, compared to ordinary FPGAs. However, because of the difference from FPGAs, known effective circuit mapping algorithms for FPGAs might not be easily applied for MPLDs. Consequently, architectural evaluation of MPLD has been also difficult to carry out. In order to alleviate the situation, we have designed a tool for supporting circuit mapping evaluation for MPLDs, which can also be seen as a supporting tool for evaluation of the MPLD architecture. The tool is basically a viewer with editing facility of circuits mapped onto MPLDs. The tool is designed to be applicable to any type of instance of MPLD architecture. The tool is carefully designed to be easy to browse and manipulate. The development of a prototype of the design confirmed the functionality of the tool to be appropriate for the purpose of the design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / MPLD / EDA tool / GUI |
| Paper # | RECONF2010-27 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of a GUI Tool for Circuit Design on MPLDs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | MPLD |
| Keyword(3) | EDA tool |
| Keyword(4) | GUI |
| 1st Author's Name | Ken TAOMOTO |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Hideyuki KAWABATA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Masato INAGI |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 4th Author's Name | Kazuya TANIGAWA |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 5th Author's Name | Tetsu HIRONAKA |
| 5th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 6th Author's Name | Masayuki SATO |
| 6th Author's Affiliation | Taiyo Yuden Co.,Ltd. |
| 7th Author's Name | Takashi ISHIGURO |
| 7th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 8th Author's Name | Toshiaki KITAMURA |
| 8th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2010-09-16 |
| Paper # | RECONF2010-27 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |