Presentation 2010-09-16
An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs
Masatoshi NAKAMURA, Masato INAGI, Kazuya TANIGAWA, Tetsuo HIRONAKA, Masayuki SATO, Takashi ISHIGURO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we propose a placement and routing method for a reconfigurable device MPLD. MPLD consists of MLUTs which can be used as logic elements and/or wire elements, whareas an FPGA consists of LUTs (logic elements) and switchboxes (wire elements). MPLD aims to contain logic circuits more efficiently than FPGAs by the routing flexibility of MLUT. However, directly applying the existing placement and routing algorithms for FPGAs to MPLD overcrowds the placed logic elements. In other words, it causes the shortage of wiring domains between logic elements. Our proposed method is based on a simulated annealing based method for FPGAs and considers the wiring area in its cost function. To evaluate the effectiveness, we implemented a placement and routing tool based on our proposed method. In the evaluation, our method suppressed the wire congestion and succeeded in placing and routing logic circuits that a conventional method for FPGAs failed to place and route.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MPLD / EDA tool / placement / routing / simulated annealing
Paper # RECONF2010-26
Date of Issue

Conference Information
Committee RECONF
Conference Date 2010/9/9(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs
Sub Title (in English)
Keyword(1) MPLD
Keyword(2) EDA tool
Keyword(3) placement
Keyword(4) routing
Keyword(5) simulated annealing
1st Author's Name Masatoshi NAKAMURA
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Masato INAGI
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
3rd Author's Name Kazuya TANIGAWA
3rd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
4th Author's Name Tetsuo HIRONAKA
4th Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
5th Author's Name Masayuki SATO
5th Author's Affiliation Taiyo Yuden Co., Ltd
6th Author's Name Takashi ISHIGURO
6th Author's Affiliation Taiyo Yuden Co., Ltd
Date 2010-09-16
Paper # RECONF2010-26
Volume (vol) vol.110
Number (no) 204
Page pp.pp.-
#Pages 6
Date of Issue