| Presentation | 2010-09-16 Finite Field Arithmetic on a Reconfigurable Processor with Variable Word Size Yuichiro SHIBATA, Ryuichi HARASAWA, Kiyoshi OGURI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper discusses a speedup technique of the reduction process for finite fields with characteristic 2 (GF(2^m)), targeting for elliptic curve cryptography executed on soft processors configured with reconfigurable devices such as FPGAs. It is already known that the number of arithmetic operations required for the reduction algorithm for GF(2^m) is largely influenced by the relation between the irreducible polynomial and the word size of the processor. Inspired by this fact and making the best use of the flexibly that reconfigurable devices offer, we propose an approach to speeding up the reduction process by changing the word size according to a given irreducible polynomial and perform some experiments to discuss its effectiveness. The primary evaluation reveal that a processor with the variable word size can reduce the required arithmetic cost by up to 18% compared to standard size processors without increasing the word size. The evaluation results also show that 25% and 61% arithmetic reduction can be achieved by allowing increase in the word size by up to 10% and by selecting favorable irreducible polynomials, respectively, suggesting positive prospects for the effectiveness of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | irreducible polynomial / GF(2^m) / reduction algorithm / variable size word / reconfigurable device |
| Paper # | RECONF2010-21 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/9/9(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Finite Field Arithmetic on a Reconfigurable Processor with Variable Word Size |
| Sub Title (in English) | |
| Keyword(1) | irreducible polynomial |
| Keyword(2) | GF(2^m) |
| Keyword(3) | reduction algorithm |
| Keyword(4) | variable size word |
| Keyword(5) | reconfigurable device |
| 1st Author's Name | Yuichiro SHIBATA |
| 1st Author's Affiliation | Department of Computer and Information Sciences, Faculty of Engineering, Nagasaki University() |
| 2nd Author's Name | Ryuichi HARASAWA |
| 2nd Author's Affiliation | Department of Computer and Information Sciences, Faculty of Engineering, Nagasaki University |
| 3rd Author's Name | Kiyoshi OGURI |
| 3rd Author's Affiliation | Department of Computer and Information Sciences, Faculty of Engineering, Nagasaki University |
| Date | 2010-09-16 |
| Paper # | RECONF2010-21 |
| Volume (vol) | vol.110 |
| Number (no) | 204 |
| Page | pp.pp.- |
| #Pages | 6 |
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