Presentation | 2010-09-16 Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration Hiroyuki KAWAI, Moritoshi YASUNAGA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we develop an on-chip pattern recognition system. The feature of this system is that two Microblaze cores are implemented on an FPGA and it can execute evolutionary algorithm faster than the past system. As an experiment, sonar spectrum pattern recognition which is a real-world problem is adopted and our developed system is evaluated with the problem. We show that our system can execute evolutionary computing approximately 2 times faster than the past system and deal with a real-world application. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / Dynamic and Partial Reconfiguration / On-chip system / Multi-core CPU / Evolvable Hardware |
Paper # | RECONF2010-18 |
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Committee | RECONF |
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Conference Date | 2010/9/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | Dynamic and Partial Reconfiguration |
Keyword(3) | On-chip system |
Keyword(4) | Multi-core CPU |
Keyword(5) | Evolvable Hardware |
1st Author's Name | Hiroyuki KAWAI |
1st Author's Affiliation | University of Tsukuba, Department of Systems and Information Engineering() |
2nd Author's Name | Moritoshi YASUNAGA |
2nd Author's Affiliation | University of Tsukuba, Department of Systems and Information Engineering |
Date | 2010-09-16 |
Paper # | RECONF2010-18 |
Volume (vol) | vol.110 |
Number (no) | 204 |
Page | pp.pp.- |
#Pages | 6 |
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