| Presentation | 2010-10-29 Prototyping and Performance Evaluation of LDPC-MMSE-SIC System with Time Interleaving Kazuhiko MITSUYAMA, Kohei KAMBARA, Takayuki NAKAGAWA, Tetsuomi IKEDA, Tomoaki OHTSUKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | LDPC-MMSE-SIC, which exploits turbo equalization combined error correcting using LDPC codes with MMSE filtering, is a powerful detection and decoding scheme in MIMO transmission. We have proposed an architecture for LDPC-MMSE-SIC systems that can apply time interleaving without significant processing latency so far. Now, we have developed a LDPC-MMSE-SIC prototype system for 2×2 MIMO-OFDM to evaluate the processing latency on turbo iterations and its transmission performance in various channels. The prototype system was confirmed to be able to implement turbo iterations with lower latency than one fortieth of time interleaving length used in our FPU systems. Furthermore, an indoor experiment was conducted using a fading simulator, and computer simulation was also executed to evaluate its validity. As a result, the bit error rate performance was confirmed to be greatly improved by turbo iterations both in flat fading and frequency selective channels when time interleaving was applied. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MIMO / LDPC-MMSE-SIC / time interleaving / prototyping / processing latency / indoor experiment |
| Paper # | RCS2010-130 |
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| Committee | RCS |
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| Conference Date | 2010/10/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Radio Communication Systems (RCS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Prototyping and Performance Evaluation of LDPC-MMSE-SIC System with Time Interleaving |
| Sub Title (in English) | |
| Keyword(1) | MIMO |
| Keyword(2) | LDPC-MMSE-SIC |
| Keyword(3) | time interleaving |
| Keyword(4) | prototyping |
| Keyword(5) | processing latency |
| Keyword(6) | indoor experiment |
| 1st Author's Name | Kazuhiko MITSUYAMA |
| 1st Author's Affiliation | Science and Technology Research Laboratories, NHK:Science and Technology, Keio University() |
| 2nd Author's Name | Kohei KAMBARA |
| 2nd Author's Affiliation | Science and Technology Research Laboratories, NHK |
| 3rd Author's Name | Takayuki NAKAGAWA |
| 3rd Author's Affiliation | Science and Technology Research Laboratories, NHK |
| 4th Author's Name | Tetsuomi IKEDA |
| 4th Author's Affiliation | Science and Technology Research Laboratories, NHK |
| 5th Author's Name | Tomoaki OHTSUKI |
| 5th Author's Affiliation | Science and Technology, Keio University |
| Date | 2010-10-29 |
| Paper # | RCS2010-130 |
| Volume (vol) | vol.110 |
| Number (no) | 251 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |