| Presentation | 2010-10-19 High-Speed Test of Circuit Components of SFQ Radix-2 Butterfly Processor using 10kA/cm^2 Nb Process Fumishige MIYAOKA, Yasuhiro SHIMAMURA, Toshiki KAINUMA, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A large amount of data processing at extremely high speed is necessary in real-time FFT (Fast Fourier Transform). However, the power consumption will be serious problems when implementing FFT processors using CMOS circuits. Single flux quantum (SFQ) circuits have potential to solve the problem because of its ultra low power consumption and high-speed operation. Until now, we designed and implemented a radix-2 butterfly unit for the FFT processor using ISTEC standard process 2 (2.5kA/cm^2 Nb Process), and successfully verified its high-speed operations at 25GHz. In this study, we designed and implemented circuit components of the radix-2 butterfly unit, adder, subtractor and multiplier, using ISTEC advanced process 2.2 (10kA/cm^2 Nb process). All circuit components successfully operated at about 100GHz and measured results agree well with simulation results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ / FFT / butterfly processing unit / superconductive integrated circuit / adder / multiplier |
| Paper # | SCE2010-34 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2010/10/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Speed Test of Circuit Components of SFQ Radix-2 Butterfly Processor using 10kA/cm^2 Nb Process |
| Sub Title (in English) | |
| Keyword(1) | SFQ |
| Keyword(2) | FFT |
| Keyword(3) | butterfly processing unit |
| Keyword(4) | superconductive integrated circuit |
| Keyword(5) | adder |
| Keyword(6) | multiplier |
| 1st Author's Name | Fumishige MIYAOKA |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Yasuhiro SHIMAMURA |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Toshiki KAINUMA |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Yuki YAMANASHI |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 5th Author's Name | Nobuyuki YOSHIKAWA |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| Date | 2010-10-19 |
| Paper # | SCE2010-34 |
| Volume (vol) | vol.110 |
| Number (no) | 235 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |