Presentation 2010-10-27
Performance Analysis of Sigma-delta ADC With Fractional Sample Rate Conversion
Akira TANAKA, Mamiko INAMORI, Yukitoshi SANADA,
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Abstract(in English) This work presents a sigma-delta analog-to-digital converter (ADC) with Fractional Sample Rate Conversion (SRC). Our previous report proposed a fractional sample rate conversion by direct insertion/deletion method. However, the method requires a lowpass filter be placed after the sigma-delta modulator. The proposed method in this report realizes SRC and low speed lowpass filter by decimating the sigma-delta modulated signal before a FIR lowpass filter. Simulation results show that the current proposed method achieves similar performance as conventional methods but at a lower adder clock speed.
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Keyword(in English) fractional SRC / sigma-delta A/D / SDR / direct insertion/deletion
Paper # SR2010-40
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Conference Date 2010/10/20(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Analysis of Sigma-delta ADC With Fractional Sample Rate Conversion
Sub Title (in English)
Keyword(1) fractional SRC
Keyword(2) sigma-delta A/D
Keyword(3) SDR
Keyword(4) direct insertion/deletion
1st Author's Name Akira TANAKA
1st Author's Affiliation Dept. of Electronics and Electrical Engineering, Keio University()
2nd Author's Name Mamiko INAMORI
2nd Author's Affiliation Dept. of Electronics and Electrical Engineering, Keio University
3rd Author's Name Yukitoshi SANADA
3rd Author's Affiliation Dept. of Electronics and Electrical Engineering, Keio University
Date 2010-10-27
Paper # SR2010-40
Volume (vol) vol.110
Number (no) 252
Page pp.pp.-
#Pages 6
Date of Issue