| Presentation | 2010/8/19 Development of sub-10μm Thinning Technology using Actual Device Wafers Nobuhide Maeda, Young Suk Kim, Yoshinobu Hikosaka, Takashi Eshita, Hideki Kitada, Koji Fujimoto, Yoriko Mizushima, Kousuke Suzuki, Tomoji Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | 200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-μm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to < 10-μm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Wafer thinning / 3D Integration |
| Paper # | ICD2010-56,SDM2010-141 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2010/8/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of sub-10μm Thinning Technology using Actual Device Wafers |
| Sub Title (in English) | |
| Keyword(1) | Wafer thinning |
| Keyword(2) | 3D Integration |
| 1st Author's Name | Nobuhide Maeda |
| 1st Author's Affiliation | School of Engineering, The University of Tokyo() |
| 2nd Author's Name | Young Suk Kim |
| 2nd Author's Affiliation | School of Engineering, The University of Tokyo |
| 3rd Author's Name | Yoshinobu Hikosaka |
| 3rd Author's Affiliation | Fujitsu Semiconductor Ltd. |
| 4th Author's Name | Takashi Eshita |
| 4th Author's Affiliation | Fujitsu Semiconductor Ltd. |
| 5th Author's Name | Hideki Kitada |
| 5th Author's Affiliation | School of Engineering, The University of Tokyo |
| 6th Author's Name | Koji Fujimoto |
| 6th Author's Affiliation | School of Engineering, The University of Tokyo |
| 7th Author's Name | Yoriko Mizushima |
| 7th Author's Affiliation | Dai Nippon Printing |
| 8th Author's Name | Kousuke Suzuki |
| 8th Author's Affiliation | Fujitsu Laboratories Ltd. |
| 9th Author's Name | Tomoji Nakamura |
| 9th Author's Affiliation | Dai Nippon Printing |
| 10th Author's Name | Akihito Kawai |
| 10th Author's Affiliation | DISCO Corporation. |
| 11th Author's Name | Kazuhisa Arai |
| 11th Author's Affiliation | DISCO Corporation. |
| 12th Author's Name | Takayuki Ohba |
| 12th Author's Affiliation | School of Engineering, The University of Tokyo |
| Date | 2010/8/19 |
| Paper # | ICD2010-56,SDM2010-141 |
| Volume (vol) | vol.110 |
| Number (no) | 183 |
| Page | pp.pp.- |
| #Pages | 3 |
| Date of Issue | |