| Presentation | 2010/8/19 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu YANAGAWA, Kazuo ONO, Akira KOTABE, Tomonori SEKIGUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques; 1)5-stage pipelined 16-DRAM cores, 2)an early bar write scheme for an 8-ns cycle-array operation, 3)16-Gbit/s I/O circuit on each 32 through-silicon-via pairs/DRAM core. We confirmed by the circuit simulation assuming 45-nm 1-Gbit chip that the proposed architecture achieves 1-Tbyte/s bandwidth with 19.5-W power consumption. The chip area is estimated to be 52mm^2. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / 3-D interconnect / through silicon via / throughput computing |
| Paper # | ICD2010-46,SDM2010-131 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2010/8/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | 3-D interconnect |
| Keyword(3) | through silicon via |
| Keyword(4) | throughput computing |
| 1st Author's Name | Yoshimitsu YANAGAWA |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Kazuo ONO |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | Akira KOTABE |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 4th Author's Name | Tomonori SEKIGUCHI |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2010/8/19 |
| Paper # | ICD2010-46,SDM2010-131 |
| Volume (vol) | vol.110 |
| Number (no) | 183 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |