| Presentation | 2010/8/19 10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects Takuji MIKI, Takashi MORIE, Toshiaki OZEKI, Shiro DOSHO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes an on-chip digital calibration technique to eliminate a memory effect error in Double-sampling Pipelined Analog to Digital Converters. In double-sampling pipelined ADC, one channel's output is affected by the other channel's adjacent output due to share an Op-amp with 2-channel Pipelined ADCs. To avoid this memory effect error, high gain Op-amp is required in conventional technique, but it causes high power consumption and large area of ADC. Therefore, we developed digital memory effect calibration techniques without using a high gain Op-amp. Since this technique fully performs in digital domain, power consumption and area of pipelined ADC becomes lower and smaller as miniaturization of CMOS process. This paper shows 10-bit 300MHz double-sampling pipelined ADC with on-chip digital calibration for memory effects fabricated with 45nm CMOS. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Pipelined ADCs / Double-sampling / Memory effect / Digital calibration |
| Paper # | ICD2010-44,SDM2010-129 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2010/8/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects |
| Sub Title (in English) | |
| Keyword(1) | Pipelined ADCs |
| Keyword(2) | Double-sampling |
| Keyword(3) | Memory effect |
| Keyword(4) | Digital calibration |
| 1st Author's Name | Takuji MIKI |
| 1st Author's Affiliation | Strategic Semiconductor Development Center, Panasonic Corporation() |
| 2nd Author's Name | Takashi MORIE |
| 2nd Author's Affiliation | Strategic Semiconductor Development Center, Panasonic Corporation |
| 3rd Author's Name | Toshiaki OZEKI |
| 3rd Author's Affiliation | Strategic Semiconductor Development Center, Panasonic Corporation |
| 4th Author's Name | Shiro DOSHO |
| 4th Author's Affiliation | Strategic Semiconductor Development Center, Panasonic Corporation |
| Date | 2010/8/19 |
| Paper # | ICD2010-44,SDM2010-129 |
| Volume (vol) | vol.110 |
| Number (no) | 183 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |