| Presentation | 2010/8/19 On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores Utilizing Parasitic Capacitance of Sleep Block Jinmyoung KIM, Toru NAKURA, Hidehiro TAKATA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an on-chip supply resonance noise reduction method for multi-IP cores utilizing parasitic capacitance of sleep blocks. It has smaller area penalty than conventional on-chip large MOS capacitors because we use parasitic capacitance of sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18μm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast power mode transition possible for dynamic voltage scaling and power gating. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Resonant supply noise / Rush current / Parasitic Capacitor / Sleep Block / Signal Integrity |
| Paper # | ICD2010-39,SDM2010-124 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2010/8/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores Utilizing Parasitic Capacitance of Sleep Block |
| Sub Title (in English) | |
| Keyword(1) | Resonant supply noise |
| Keyword(2) | Rush current |
| Keyword(3) | Parasitic Capacitor |
| Keyword(4) | Sleep Block |
| Keyword(5) | Signal Integrity |
| 1st Author's Name | Jinmyoung KIM |
| 1st Author's Affiliation | Dept. of Electrical Engineering, the University of Tokyo() |
| 2nd Author's Name | Toru NAKURA |
| 2nd Author's Affiliation | VLSI Design and Education Center, the University of Tokyo |
| 3rd Author's Name | Hidehiro TAKATA |
| 3rd Author's Affiliation | Design Platform Development Division, Renesas Electronics Corporation |
| 4th Author's Name | Koichiro ISHIBASHI |
| 4th Author's Affiliation | Design Platform Development Division, Renesas Electronics Corporation |
| 5th Author's Name | Makoto IKEDA |
| 5th Author's Affiliation | Dept. of Electrical Engineering, the University of Tokyo:VLSI Design and Education Center, the University of Tokyo |
| 6th Author's Name | Kunihiro ASADA |
| 6th Author's Affiliation | Dept. of Electrical Engineering, the University of Tokyo:VLSI Design and Education Center, the University of Tokyo |
| Date | 2010/8/19 |
| Paper # | ICD2010-39,SDM2010-124 |
| Volume (vol) | vol.110 |
| Number (no) | 183 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |