Presentation 2010-07-23
On-chip background calibration of time-interleaved ADC
Takashi Oshima, Tomomi Takahashi,
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Abstract(in English) An extremely-high-speed high-resolution time-interleaved ADC is a key enabler of the next-generation applications. The gain, offset and sampling-timing mismatches among unit ADCs of a time-interleaved ADC are compensated by the proposed background calibration, which is simple enough to be implemented on a single chip.
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Keyword(in English) time-interleaved ADC / digital calibration / mismatch / LMS algorithm / skew
Paper # ICD2010-34
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Committee ICD
Conference Date 2010/7/15(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On-chip background calibration of time-interleaved ADC
Sub Title (in English)
Keyword(1) time-interleaved ADC
Keyword(2) digital calibration
Keyword(3) mismatch
Keyword(4) LMS algorithm
Keyword(5) skew
1st Author's Name Takashi Oshima
1st Author's Affiliation Central Research Laboratory, HITACHI Ltd.()
2nd Author's Name Tomomi Takahashi
2nd Author's Affiliation Central Research Laboratory, HITACHI Ltd.
Date 2010-07-23
Paper # ICD2010-34
Volume (vol) vol.110
Number (no) 140
Page pp.pp.-
#Pages 6
Date of Issue