Presentation 2010-07-23
OTA Design Using g_m/I_D Lookup Table Methodology : Design optimization featuring Settling Time analysis
Toru KASHIMURA, Takayuki KONISHI, Shoichi MASUI,
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Abstract(in English) Settling Time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applications such as pipeline AD converters. For scaled CMOS technologies, an OTA design methodology using g_m/I_D lookup tables has been proposed to minimize its power consumption. A major problem in the conventionally proposed method is that Settling Time was not included in a target specification, but was converted into crossover frequency f_c with an empirical approach. In this paper, we introduce an iterative optimization sequence to design OTAs, which can achieve the target Settling Time with the minimum power consumptions.
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Keyword(in English) operational transconductance amplifier / design optimization / Settling Time optimization / low power design
Paper # ICD2010-31
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Conference Date 2010/7/15(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) OTA Design Using g_m/I_D Lookup Table Methodology : Design optimization featuring Settling Time analysis
Sub Title (in English)
Keyword(1) operational transconductance amplifier
Keyword(2) design optimization
Keyword(3) Settling Time optimization
Keyword(4) low power design
1st Author's Name Toru KASHIMURA
1st Author's Affiliation Tohoku University()
2nd Author's Name Takayuki KONISHI
2nd Author's Affiliation Tohoku University
3rd Author's Name Shoichi MASUI
3rd Author's Affiliation Tohoku University
Date 2010-07-23
Paper # ICD2010-31
Volume (vol) vol.110
Number (no) 140
Page pp.pp.-
#Pages 6
Date of Issue