| Presentation | 2010-07-23 Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply Tomochika HARADA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, an 0.5V analog amplifier circuit using only sub-μA order subthreshold current for realizing ultra-low power analog/digital LSI system by using low output power supply, such as a battery, solar cell, and MEMS type power plant, is presented. In this circuit, it is designed and fabricated using double-well or triple-well structure 65nm CMOS process, and this circuit is estimated for subthreshold analog circuit characteristics and circuit design using body effect and the other short channel effect in subthreshold region. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | subthreshold region / ultra-low voltage / analog circuit |
| Paper # | ICD2010-30 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2010/7/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply |
| Sub Title (in English) | |
| Keyword(1) | subthreshold region |
| Keyword(2) | ultra-low voltage |
| Keyword(3) | analog circuit |
| 1st Author's Name | Tomochika HARADA |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Yamagata University() |
| Date | 2010-07-23 |
| Paper # | ICD2010-30 |
| Volume (vol) | vol.110 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |