| Presentation | 2010-07-22 A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter Tadashi MAEDA, Takashi TOKAIRIN, Masaki KITSUNEZUKA, Mitsuji OKADA, Muneo FUKAISHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a 2-step structure with an inverter- and a vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of -105 dBc/Hz, where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of -115 dBc/Hz at a 1-MHz offset frequency. The chip core occupies 0.37mm^2 and the measured power consumption is 8.1 mA from a 1.2-V power supply. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | All-digital phase locked loop(ADPLL) / digitally controlled oscillator(DCO) / frequency synthesizer / phase noise / quantization noise / time-to-digital converter(TDC) / Σ△ modulator / synchronous counter / higher-order modulation |
| Paper # | ICD2010-29 |
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| Committee | ICD |
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| Conference Date | 2010/7/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter |
| Sub Title (in English) | |
| Keyword(1) | All-digital phase locked loop(ADPLL) |
| Keyword(2) | digitally controlled oscillator(DCO) |
| Keyword(3) | frequency synthesizer |
| Keyword(4) | phase noise |
| Keyword(5) | quantization noise |
| Keyword(6) | time-to-digital converter(TDC) |
| Keyword(7) | Σ△ modulator |
| Keyword(8) | synchronous counter |
| Keyword(9) | higher-order modulation |
| 1st Author's Name | Tadashi MAEDA |
| 1st Author's Affiliation | Advanced LSI Systems Research, LSI research Laboratory, Renesas Electronics Corporation() |
| 2nd Author's Name | Takashi TOKAIRIN |
| 2nd Author's Affiliation | Advanced LSI Systems Research, LSI research Laboratory, Renesas Electronics Corporation |
| 3rd Author's Name | Masaki KITSUNEZUKA |
| 3rd Author's Affiliation | System IP-core Laboratory, NEC Corporation |
| 4th Author's Name | Mitsuji OKADA |
| 4th Author's Affiliation | Advanced LSI Systems Research, LSI research Laboratory, Renesas Electronics Corporation |
| 5th Author's Name | Muneo FUKAISHI |
| 5th Author's Affiliation | System IP-core Laboratory, NEC Corporation |
| Date | 2010-07-22 |
| Paper # | ICD2010-29 |
| Volume (vol) | vol.110 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |