Presentation 2010-07-22
Digitally-Assisted Analog Test Technology : Analog Circuit Test Technology in Nano-CMOS Era
Haruo KOBAYASHI, Takahiro J. YAMAGUCHI,
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Abstract(in English) This paper reviews current production testing issues for analog and mixed-signal SoC, and discusses the following: (i)Digitally-assisted analog technology prevails in mixed-signal SoC with fine CMOS which uses digital-rich architecture, digital self-calibration and error correction, and we consider their effective production testing. (ii)Mixed-signal SoCs frequently incorporate digital resources such as DSP cores and memory. We discuss how such resources can be utilized to simplify production testing of the analog RF circuitry in the SoC.
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Keyword(in English) Digitally-Assisted Analog Technology / Digitally-Assisted Analog Test Technology / Design for Testability / Self-Calibration / Digital Error Correction
Paper # ICD2010-27
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Conference Date 2010/7/15(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Digitally-Assisted Analog Test Technology : Analog Circuit Test Technology in Nano-CMOS Era
Sub Title (in English)
Keyword(1) Digitally-Assisted Analog Technology
Keyword(2) Digitally-Assisted Analog Test Technology
Keyword(3) Design for Testability
Keyword(4) Self-Calibration
Keyword(5) Digital Error Correction
1st Author's Name Haruo KOBAYASHI
1st Author's Affiliation Dept. of Electronic Engineering, Gunma University()
2nd Author's Name Takahiro J. YAMAGUCHI
2nd Author's Affiliation Dept. of Electronic Engineering, Gunma University
Date 2010-07-22
Paper # ICD2010-27
Volume (vol) vol.110
Number (no) 140
Page pp.pp.-
#Pages 6
Date of Issue