Presentation | 2010-07-22 Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect Tetsuya IIZUKA, Toru NAKURA, Kunihiro ASADA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias temperature instability (NBTI/PBTI). |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | variability / aging effects / on-chip monitor / buffer ring / NBTI / PBTI |
Paper # | ICD2010-24 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2010/7/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect |
Sub Title (in English) | |
Keyword(1) | variability |
Keyword(2) | aging effects |
Keyword(3) | on-chip monitor |
Keyword(4) | buffer ring |
Keyword(5) | NBTI |
Keyword(6) | PBTI |
1st Author's Name | Tetsuya IIZUKA |
1st Author's Affiliation | VLSI Design and Education Center (VDEC), University of Tokyo() |
2nd Author's Name | Toru NAKURA |
2nd Author's Affiliation | VLSI Design and Education Center (VDEC), University of Tokyo |
3rd Author's Name | Kunihiro ASADA |
3rd Author's Affiliation | VLSI Design and Education Center (VDEC), University of Tokyo:Dept. of Electrical Engineering and Information Systems, University of Tokyo |
Date | 2010-07-22 |
Paper # | ICD2010-24 |
Volume (vol) | vol.110 |
Number (no) | 140 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |