| Presentation | 2010-08-26 Pull-up/pull-down circuits with no static current consumption Tatsuya UENO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, pull-up/pull-down circuits with no static current consumption are reported. The pull-up/pull-down circuits are configured with FET for tri-state I/O ports. The minimum configuration is only 5 FETs. By using the pull-up/pull-down circuit, undefined level problem caused at power-on due to the use of a bus-hold circuit instead of a pull-up/pull-down resistor can be avoided. It was confirmed that this circuit operated correctly with a custom IC. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Pull-up/Pull-down Circuit / Static Current Consumption |
| Paper # | SDM2010-130,ICD2010-45 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2010/8/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Pull-up/pull-down circuits with no static current consumption |
| Sub Title (in English) | |
| Keyword(1) | Pull-up/Pull-down Circuit |
| Keyword(2) | Static Current Consumption |
| 1st Author's Name | Tatsuya UENO |
| 1st Author's Affiliation | Yamatake Corporation() |
| Date | 2010-08-26 |
| Paper # | SDM2010-130,ICD2010-45 |
| Volume (vol) | vol.110 |
| Number (no) | 182 |
| Page | pp.pp.- |
| #Pages | 3 |
| Date of Issue | |