Presentation 2010/7/28
Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code
Yoshito SAKAGUCHI, Mochamad ASRI, Shinya TAKAMAEDA, Haruhiko KANEKO, Kenji KISE,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Errror correcting code is required, which is capable enough of correctiong errors, implementable with low resources and highspeed. Sawa proposed a code to achieve these requirements. We focus on this code. We implement the encoder and the decoder on FPGAs and evaluate the code. The result shows that the decoder can be implimented with 260 of 4 input LUTs, the code is decodable in 3 cycles and acheives lower error rate than SEC-DED (sigle error correction - double error detection) code.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / ECC / serial communications
Paper # CPSY2010-19
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Committee CPSY
Conference Date 2010/7/28(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementaton and evaluation of light weight high speed serial communications with Error Correcting Code
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) ECC
Keyword(3) serial communications
1st Author's Name Yoshito SAKAGUCHI
1st Author's Affiliation Tokyo Institute of Technology()
2nd Author's Name Mochamad ASRI
2nd Author's Affiliation Tokyo Institute of Technology
3rd Author's Name Shinya TAKAMAEDA
3rd Author's Affiliation Tokyo Institute of Technology
4th Author's Name Haruhiko KANEKO
4th Author's Affiliation Tokyo Institute of Technology
5th Author's Name Kenji KISE
5th Author's Affiliation Tokyo Institute of Technology
Date 2010/7/28
Paper # CPSY2010-19
Volume (vol) vol.110
Number (no) 167
Page pp.pp.-
#Pages 6
Date of Issue