Presentation | 2010/7/28 A Consideration on Speculative Memory Access in Two-Path Limited Speculation System Hiroyoshi JUTORI, Akihiro FUKUDA, Tsubasa TSUDA, Kanemitsu OOTSU, Takashi YOKOTA, Takanobu BABA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We have proposed two-path limited speculation method and a multi-core processor architecture PALS which based on the method. In this method, two paths of the highest execution frequency are speculatively executed for speed-up of program's loop. In this paper, we investigate the minimum entry required for Memory Buffer (MB) that structures memory access mechanism in the PALS architecture. Since the mechanism requires large hardware cost in the PALS architecture. And we also consider code optimization technique for the loops that include inter-memory dependence. We show that MB requires 24 entries by evaluating the number of store instructions in the loops of SPEC CPU2000 and MediaBench programs. We achieved about 250% speed-up by moving load instructions which are cause of inter-memory dependence to outside of loops. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | multi-core processor / speculative multithreading / speculative memory access / two-path limited speculation method |
Paper # | CPSY2010-18 |
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Conference Information | |
Committee | CPSY |
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Conference Date | 2010/7/28(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Computer Systems (CPSY) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Consideration on Speculative Memory Access in Two-Path Limited Speculation System |
Sub Title (in English) | |
Keyword(1) | multi-core processor |
Keyword(2) | speculative multithreading |
Keyword(3) | speculative memory access |
Keyword(4) | two-path limited speculation method |
1st Author's Name | Hiroyoshi JUTORI |
1st Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University() |
2nd Author's Name | Akihiro FUKUDA |
2nd Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University |
3rd Author's Name | Tsubasa TSUDA |
3rd Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University |
4th Author's Name | Kanemitsu OOTSU |
4th Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University |
5th Author's Name | Takashi YOKOTA |
5th Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University |
6th Author's Name | Takanobu BABA |
6th Author's Affiliation | Information Systems Science, Graduate School of Engineering, Utsunomiya University |
Date | 2010/7/28 |
Paper # | CPSY2010-18 |
Volume (vol) | vol.110 |
Number (no) | 167 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |