| Presentation | 2010-07-15 Effective Position of Decoupling Inductor Taking Parasitic Capacitances on Power Distribution Network Traces into Account Yusuke YANO, Kengo IOKIBE, Yoshitaka TOYOTA, Ryuji KOGA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | High-frequency current caused by simultaneous switching of digital gates can be increased with decoupling capacitors, because equivalent series inductance (ESL) of the decoupling capacitors makes resonance with parasitic capacitance on power distribution network trace. In this report, we discussed the location of decoupling inductors as a countermeasure and to reduce the high frequency power current by a circuit simulation. We employed a four-layered printed circuit board as a device under test. The board included an oscillation circuit with a versatile inverter IC and a power distribution network. The board was modeled with a linear equivalent circuit and a current source (LECCS) for the circuit simulations of the RF powe current and power bounce. Results of the circuit simulations showed that reduction of the RF power current was larger with a decoupling inductor placed between the decoupling capacitor and the parasitic capacitance than out side the parasitic capacitance, though a peak current could be occur due to a resonance the parasitic capacitance contributed. The RF power current was reduced at all frequencies even when the decoupling inductor was placed outside the parasitic capacitance. In addition, in order to investigate influence on power integrity (PI) performance of the IC, potential difference between power terminals of chip was calculated. The simulation results showed that the decoupling inductors caused trivial deterioration in P1 performance of the IC. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Decoupling capacitor / Decoupling Inductor / Parasitic Capacitor / IC / EMC / RF power current / LECOS |
| Paper # | EMCJ2010-28 |
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| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2010/7/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electromagnetic Compatibility (EMCJ) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effective Position of Decoupling Inductor Taking Parasitic Capacitances on Power Distribution Network Traces into Account |
| Sub Title (in English) | |
| Keyword(1) | Decoupling capacitor |
| Keyword(2) | Decoupling Inductor |
| Keyword(3) | Parasitic Capacitor |
| Keyword(4) | IC |
| Keyword(5) | EMC |
| Keyword(6) | RF power current |
| Keyword(7) | LECOS |
| 1st Author's Name | Yusuke YANO |
| 1st Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University() |
| 2nd Author's Name | Kengo IOKIBE |
| 2nd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 3rd Author's Name | Yoshitaka TOYOTA |
| 3rd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 4th Author's Name | Ryuji KOGA |
| 4th Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| Date | 2010-07-15 |
| Paper # | EMCJ2010-28 |
| Volume (vol) | vol.110 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |