| Presentation | 2010-07-22 50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm^2 Nb Advanced Process Yasuhiro Shimamura, Toshiki Kainuma, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been developing a large-scale reconfigurable data-path (LSRDP) using single-flux-quantum (SFQ) circuit to realize high-end computer systems. The LSRDP is composed of a large number of floating-point units (FPUs) and reconfigurable routing network switches. Because the data are directly transferred between FPUs without memory accesses in the LSRDP, the memory access rate can be ameliorated. A floating-point multiplier (FPM) is one of the main circuit components of the LSRDP. In the previous study, the half-precision FPM was designed using the ISTEC 2.5 kA/cm^2Nb standard process and its complete operation was demonstrated at 31 GHz. Recently, to make further large SFQ circuits with enhanced performance, the ISTEC 10 kA/cm^2Nb advanced process (ADP 2.1) has been developed. in this study, we have designed and implemented the 4-bit bit-serial FPM using the ADP 2.1 process. Their high-speed operations were examined by on-chip high-speed tests. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ circuit / Nb process / Floating-point multiplier / Reconfigurable data-path |
| Paper # | SCE2010-22 |
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| Committee | SCE |
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| Conference Date | 2010/7/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm^2 Nb Advanced Process |
| Sub Title (in English) | |
| Keyword(1) | SFQ circuit |
| Keyword(2) | Nb process |
| Keyword(3) | Floating-point multiplier |
| Keyword(4) | Reconfigurable data-path |
| 1st Author's Name | Yasuhiro Shimamura |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Toshiki Kainuma |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Fumishige Miyaoka |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Yuki Yamanashi |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 5th Author's Name | Nobuyuki Yoshikawa |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 6th Author's Name | Akira Fujimaki |
| 6th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 7th Author's Name | Kazuyoshi Takagi |
| 7th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 8th Author's Name | Naofumi Takagi |
| 8th Author's Affiliation | Department of Communications and Computer Engineering, Kyoko University |
| Date | 2010-07-22 |
| Paper # | SCE2010-22 |
| Volume (vol) | vol.110 |
| Number (no) | 139 |
| Page | pp.pp.- |
| #Pages | 6 |
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