Presentation 2010-07-22
Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka KITO, Masamitsu TANAKA, Kazuyoshi TAKAGI, Naofumi TAKAGI,
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Abstract(in English) This report discusses fault modeling and test generation for Single Flux Quqntum (SFQ) logic circuits. SFQ circuits are very fast and use special logic system (pulse logic). Therefore, SFQ specific faults different from those in CMOS logic circuits exist such as jitter of data arrival cycle at gate inputs. This report shows a fault model for SFQ circuit specific faults and shows a test generation method with respect to it.
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Keyword(in English) Single flux quantum circuit / testing / fault diagnosis / timing fault
Paper # SCE2010-19
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Conference Information
Committee SCE
Conference Date 2010/7/15(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits
Sub Title (in English)
Keyword(1) Single flux quantum circuit
Keyword(2) testing
Keyword(3) fault diagnosis
Keyword(4) timing fault
1st Author's Name Nobutaka KITO
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Masamitsu TANAKA
2nd Author's Affiliation Graduate School of Information Science, Nagoya University
3rd Author's Name Kazuyoshi TAKAGI
3rd Author's Affiliation Graduate School of Information Science, Nagoya University
4th Author's Name Naofumi TAKAGI
4th Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2010-07-22
Paper # SCE2010-19
Volume (vol) vol.110
Number (no) 139
Page pp.pp.-
#Pages 5
Date of Issue