Presentation | 2010-03-09 SHIN : A Hardware Architecture for over 100M Neurons Real-time Neural-net Shinjiro TOYODA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | SHIN: Synchronous Hierarchical Information Network is a data transfer architecture which solves the enormous wiring issue among the over 10^8 neurons with 10^<12> synapses. At first, a virtual plane is divided into several hexagon cells. Then, the neurons in a neural-net are sprinkled into cells so that its layer formation should become vertical to the plane. Neurons in a cell can get information from neurons in the cell and neighbor cells. This architecture makes it possible to transfer information among the neurons by several local low speed signal lines. Only a signal line should be added when a new cell is applied to a system. The data transfer rate and the calculation speed of the neurons are not affected. Therefore, it is possible to make a neural-net hardware as big as we need. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | big scale neural-net / real-time operation / self-organization / spatial-divide / hardware / SHIN |
Paper # | NC2009-92 |
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Committee | NC |
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Conference Date | 2010/3/2(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Neurocomputing (NC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | SHIN : A Hardware Architecture for over 100M Neurons Real-time Neural-net |
Sub Title (in English) | |
Keyword(1) | big scale neural-net |
Keyword(2) | real-time operation |
Keyword(3) | self-organization |
Keyword(4) | spatial-divide |
Keyword(5) | hardware |
Keyword(6) | SHIN |
1st Author's Name | Shinjiro TOYODA |
1st Author's Affiliation | Honda Research Institute Japan Co., Ltd.() |
Date | 2010-03-09 |
Paper # | NC2009-92 |
Volume (vol) | vol.109 |
Number (no) | 461 |
Page | pp.pp.- |
#Pages | 6 |
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