Presentation 2010-03-10
Discreat Time Inverse Function Delayed Network with Higher-Order Connections
Takahiro SOTA, Koji KUROSE, Yoshihiro HAYAKAWA, Shigeo SATO, Koji NAKAJIMA,
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Abstract(in English) The Inverse function Delayed network with higher-order connection (HCID network) has been proposed to solve combinatorial optimization problems by using Inverse function Delayed model, which is one of the neuron models. The HCID network has quartic energy function. This quartic energy function is useful for solving the combinatorial optimization problems, because the equilibrium points of optimal solution states (the global minimum states) are correspond to vertexes of output space. Hence the HCID network can converges to only optimal solutions by destabilizing the network states except the vertexes of the output space with the negative resistance effects of the Inverse function Delayed model. However, the iteration times of simulation increase with increasing the higher-order connection, so it is necessary to use a hardware network to solve big size problems. In this report, therefore, we propose the discrete time HCID network as the preparation of hardware implementation. Moreover it is shown that this discrete time HCID network operates in the same way as the continuous time network.
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Keyword(in English) Neural network / Combinatorial optimization problem / Higher-order synaptic connection / Energy function / Negative resistance
Paper # NLP2009-181
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Conference Information
Committee NLP
Conference Date 2010/3/2(1days)
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Paper Information
Registration To Nonlinear Problems (NLP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Discreat Time Inverse Function Delayed Network with Higher-Order Connections
Sub Title (in English)
Keyword(1) Neural network
Keyword(2) Combinatorial optimization problem
Keyword(3) Higher-order synaptic connection
Keyword(4) Energy function
Keyword(5) Negative resistance
1st Author's Name Takahiro SOTA
1st Author's Affiliation Laboratory for Brainware, Laboratory for Nanoelectronics and Spintronics Research Inistiute of Electrical Communication, Tohoku University()
2nd Author's Name Koji KUROSE
2nd Author's Affiliation Laboratory for Brainware, Laboratory for Nanoelectronics and Spintronics Research Inistiute of Electrical Communication, Tohoku University
3rd Author's Name Yoshihiro HAYAKAWA
3rd Author's Affiliation Sendai National College of Technology
4th Author's Name Shigeo SATO
4th Author's Affiliation Laboratory for Brainware, Laboratory for Nanoelectronics and Spintronics Research Inistiute of Electrical Communication, Tohoku University
5th Author's Name Koji NAKAJIMA
5th Author's Affiliation Laboratory for Brainware, Laboratory for Nanoelectronics and Spintronics Research Inistiute of Electrical Communication, Tohoku University
Date 2010-03-10
Paper # NLP2009-181
Volume (vol) vol.109
Number (no) 458
Page pp.pp.-
#Pages 6
Date of Issue