Presentation | 2010-03-05 A Design Scheme for LDPC Convolutional Codes Based on Parity Check Polynomials with a Time Period of 2 Yutaka MURAKAMI, Shutai OKAMURA, Shozo OKASAKA, Takaaki KISHIGAMI, Masayuki ORIHASHI, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Low-density parity-check (LDPC) codes have attracted a lot of attention in recent years, because LDPC codes a significant outcome of channel capacity at low complexity. This paper examines a design scheme for time-varying low-density parity-check convolutional codes with a time period of 2 based on parity check polynomials (TV2-LDPC-CCs) regarding the number of short cycle. We show conditions for generating cycle of length (CL) 6 in the TV2-LDPC-CCs and examine restrictions for a search scheme for TV2-LDPC-CCs to reduce the number of CL 6. We show that a design scheme with restrictions which this paper presents can give TV2-LDPC-CCs with high error correction capacity. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | LDPC convolutional codes / A time period of 2 / Tanner graphs / Cycle of length 6 |
Paper # | RCS2009-311 |
Date of Issue |
Conference Information | |
Committee | RCS |
---|---|
Conference Date | 2010/2/24(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Radio Communication Systems (RCS) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Design Scheme for LDPC Convolutional Codes Based on Parity Check Polynomials with a Time Period of 2 |
Sub Title (in English) | |
Keyword(1) | LDPC convolutional codes |
Keyword(2) | A time period of 2 |
Keyword(3) | Tanner graphs |
Keyword(4) | Cycle of length 6 |
1st Author's Name | Yutaka MURAKAMI |
1st Author's Affiliation | Panasonic Corporation:Digital & Network Technology Development Center() |
2nd Author's Name | Shutai OKAMURA |
2nd Author's Affiliation | Panasonic Corporation:Digital & Network Technology Development Center |
3rd Author's Name | Shozo OKASAKA |
3rd Author's Affiliation | Panasonic Corporation |
4th Author's Name | Takaaki KISHIGAMI |
4th Author's Affiliation | Panasonic Corporation |
5th Author's Name | Masayuki ORIHASHI |
5th Author's Affiliation | Panasonic Corporation |
Date | 2010-03-05 |
Paper # | RCS2009-311 |
Volume (vol) | vol.109 |
Number (no) | 440 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |