| Presentation | 2010-03-04 An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA Kensuke KAWAKAMI, Koji NAKANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The main contribution of this paper is to present an efficient hardware algorithm for modular exponentiation, which is a key operation of RSA encryption/decryption. Our hardware algorithm is designed to be implemented in on the Xilinx Virtex-5 family FPGA XC5VSX50T-1, which has embedded DSP blocks (DSP48E) and embedded memory blocks (BRAM). In particular, our hardware algorithm efficiently uses these two embedded blocks such that it uses only one DSP48E block and one Block RAM for 1024-bit modular exponentiation. The implementation results showed that it runs run in no more than 44.8ms and in expected 33.8ms for 1024-bit modular exponentiation. Since it uses only one DSP48E block and one Block RAM, the FPGA can implement a lot of circuits which perform modulo exponentiation in parallel, in the same time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Modular exponentiation / Montgomery multiplication / FPGA / RSA encryption/decription / DSP block |
| Paper # | IT2009-80,ISEC2009-88,WBS2009-59 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2010/2/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An RSA Encryption Hardware Algorithm that uses a DSP block on the FPGA |
| Sub Title (in English) | |
| Keyword(1) | Modular exponentiation |
| Keyword(2) | Montgomery multiplication |
| Keyword(3) | FPGA |
| Keyword(4) | RSA encryption/decription |
| Keyword(5) | DSP block |
| 1st Author's Name | Kensuke KAWAKAMI |
| 1st Author's Affiliation | Department of Information Engineering, School of Engineering, Hiroshima University() |
| 2nd Author's Name | Koji NAKANO |
| 2nd Author's Affiliation | Department of Information Engineering, School of Engineering, Hiroshima University |
| Date | 2010-03-04 |
| Paper # | IT2009-80,ISEC2009-88,WBS2009-59 |
| Volume (vol) | vol.109 |
| Number (no) | 445 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |