| Presentation | 2010-01-28 Making and improving OTFT SPICE model utilizing devices simulation : The Format of Technical Report (Subtitle) Fumito MARUOKA, Reiji HATTORI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For the simulation of circuit including organic thin-film transistors (OTFTs), a custom device behavior model for OTFT and not for amorphous silicon or polycrystalline silicon TFT is desired. In this paper, we discussed how to model the contact resistances which have the special voltage dependence at OTFT source-drain electrodes, and the validity of the model. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | OTFT / Verilog-A / Device modeling / Schottky Barrier / Poole-Frenkel Effect |
| Paper # | EID2009-51 |
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| Conference Information | |
| Committee | EID |
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| Conference Date | 2010/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electronic Information Displays (EID) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Making and improving OTFT SPICE model utilizing devices simulation : The Format of Technical Report (Subtitle) |
| Sub Title (in English) | |
| Keyword(1) | OTFT |
| Keyword(2) | Verilog-A |
| Keyword(3) | Device modeling |
| Keyword(4) | Schottky Barrier |
| Keyword(5) | Poole-Frenkel Effect |
| 1st Author's Name | Fumito MARUOKA |
| 1st Author's Affiliation | ISEE, Kyushu University() |
| 2nd Author's Name | Reiji HATTORI |
| 2nd Author's Affiliation | KASTEC, Kyushu University |
| Date | 2010-01-28 |
| Paper # | EID2009-51 |
| Volume (vol) | vol.109 |
| Number (no) | 404 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |