| Presentation | 2010-05-19 High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation Akira OHCHI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Abstract As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. It is necessary to deal with floorplan information such as placement and interconnection delay even in high-level synthesis stage. In this paper, we propose a high-level synthesis method targeting generalized distributed-register (GDR) architecture in which we introduce shared/local registers and global/local controllers. In GDR architecture, by adding local register/controller to bottlenecked FU, we can obtain high performance circuit. By sharing register/controller between non-bottlenecked FUs, we can reduce circuit area. Our method automatically selects register/controller configuration by target application and constraints. Experimental results show that 7.6% area reduction can be achieved compared to the conventional floorplan-aware high-level synthesis method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Level Synthesis / Floorplaning / Generalized Distributed-register Architectures |
| Paper # | VLD2010-1 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2010/5/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis |
| Keyword(2) | Floorplaning |
| Keyword(3) | Generalized Distributed-register Architectures |
| 1st Author's Name | Akira OHCHI |
| 1st Author's Affiliation | Department of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Department of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Department of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Department of Computer Science and Engineering, Waseda University |
| Date | 2010-05-19 |
| Paper # | VLD2010-1 |
| Volume (vol) | vol.110 |
| Number (no) | 36 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |