講演名 2010-01-27
Effective Hardware Task Context Switching in Virtex-4 FPGAs
,
PDFダウンロードページ PDFダウンロードページへ
抄録(和)
抄録(英) A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic and partial reconfiguration, giving them additional leverage over the other co-existing FPGA solutions by allowing implementation of such concepts as a hardware task. When compared to classical software task effective employment of the new idea in preemptive multitasking systems poses many difficulties and involves many mechanisms such as context saving and restoring, to be built practically from the scratch. This paper presents an effective approach to high-speed context switching for Virtex4-based DPR (Dynamic Partial Reconfiguration) Systems based on developed embedded system infrastructure with lightweight control bus, enhancing management of reconfigurable hardware modules and very efficient, instruction-driven reconfigurationlreadback controller which offers 78-fold speed-ups and further superior functionalities when compared to baseline IP provided by FPGA's manufacturer. The whole system is additionally supported by developed bitstream manipulation tool intended for PC (Personal Computer) and used as a back-end program for current DPR design flow.
キーワード(和)
キーワード(英) FPGA / Dynamic Partial Reconfiguration / HW Context-switch
資料番号 VLD2009-87,CPSY2009-69,RECONF2009-72
発行日

研究会情報
研究会 VLD
開催期間 2010/1/19(から1日開催)
開催地(和)
開催地(英)
テーマ(和)
テーマ(英)
委員長氏名(和)
委員長氏名(英)
副委員長氏名(和)
副委員長氏名(英)
幹事氏名(和)
幹事氏名(英)
幹事補佐氏名(和)
幹事補佐氏名(英)

講演論文情報詳細
申込み研究会 VLSI Design Technologies (VLD)
本文の言語 ENG
タイトル(和)
サブタイトル(和)
タイトル(英) Effective Hardware Task Context Switching in Virtex-4 FPGAs
サブタイトル(和)
キーワード(1)(和/英) / FPGA
第 1 著者 氏名(和/英) / Krzysztof Jozwik
第 1 著者 所属(和/英)
Graduate School of Information Science, Nagoya University
発表年月日 2010-01-27
資料番号 VLD2009-87,CPSY2009-69,RECONF2009-72
巻番号(vol) vol.109
号番号(no) 393
ページ範囲 pp.-
ページ数 6
発行日