Presentation	2010-01-27 Implementation of Power Reduction with Dynamically DUa1-V_ Assignment to Dynamically Reconfigurable Processor Array Yusuke UMAHASHI, Toru SANO, Satoshi KOYAMA, Yoshiki SAITO, Hideharu AMANO, Kimiyoshi USAMI,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	We realize the reduction of executing dynamic power of Dynamically Reconfigurable Processor Array implemented Dual-V_ technique. Former, we showed effectiveness of Dual-V_ technique with gate-level simulation. In this paper, to verify more details, we designed the circuit including cells such as level-shifter cells or voltage-switching cells. We executed circuit simulation with applications and compared electric energy. We showed that electric energy was decreased 44% maximumly.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Dynamically Reconfigurable Processor / Low Power Technique / Dual-V_
Paper #	VLD2009-85,CPSY2009-67,RECONF2009-70
Date of Issue

Conference Information
Committee	VLD
Conference Date	2010/1/19(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Implementation of Power Reduction with Dynamically DUa1-V_ Assignment to Dynamically Reconfigurable Processor Array
Sub Title (in English)
Keyword(1)	Dynamically Reconfigurable Processor
Keyword(2)	Low Power Technique
Keyword(3)	Dual-V_
1st Author's Name	Yusuke UMAHASHI
1st Author's Affiliation	Graduate School of Engineering, Shibaura Institute of Technology()
2nd Author's Name	Toru SANO
2nd Author's Affiliation	Graduate School of Science and Technology, Keio University
3rd Author's Name	Satoshi KOYAMA
3rd Author's Affiliation	Graduate School of Engineering, Shibaura Institute of Technology
4th Author's Name	Yoshiki SAITO
4th Author's Affiliation	Graduate School of Science and Technology, Keio University
5th Author's Name	Hideharu AMANO
5th Author's Affiliation	Graduate School of Science and Technology, Keio University
6th Author's Name	Kimiyoshi USAMI
6th Author's Affiliation	Graduate School of Engineering, Shibaura Institute of Technology
Date	2010-01-27
Paper #	VLD2009-85,CPSY2009-67,RECONF2009-70
Volume (vol)	vol.109
Number (no)	393
Page	pp.pp.-
#Pages	6
Date of Issue