| Presentation | 2010-01-26 Reducing scheduling overheads in Dynamically Reconfigurable Processors Ratna Krishnamoorthy, Keshavan Varadarajan, Mythri Alle, Ranjani Narayan, Masahiro Fujita, S K Nandy, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Dynamically reconfigurable computing holds the promise of achieving breakthroughs that significantly enhance systems performance. Often size of a reconfigurable fabric is small when compared to application's dataflow graph. The application is broken down into smaller sub-tasks. These sub-tasks have to be sequenced based on data and control dependences for correct execution. Typically, in most of the dynamically reconfigurable processors, the overheads due to non- execution activities are quite high. The non-execution activities include (1) sequencing of sub-tasks as per data flow order (2) determining their placement on the reconfigurable fabric (3) launching them onto the reconfigurable fabric and (4) performing data exchange between sub-tasks. We use REDEFINE as our target Dynamically Reconfigurable Processor, where application sub-tasks are referred to as hyperops. In REDEFINE, the overheads of non-execution activities viz, sequencing and launching, are reported to be as high as 50% of the overall execution time. The aim of this work is to hide the latencies due to these overheads. This is done by appropriately prefetching the hyperops ahead of time, and thereby improving the overall performance. An interaction graph, which captures the control and data dependences between hyperops, is constructed. We use speculative trace scheduling method to predict the next hyperop to be prefetched. The existing REDEFINE framework is modified to include a prediction unit. Simulation results show around 12-27% reduction in overall execution time, when compared to the execution time without prefetching. This is achieved due to 31-68% reduction in overheads of sequencing and launching. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically reconfigurable processors / dynamic scheduling / prefetch / hyperop |
| Paper # | VLD2009-70,CPSY2009-52,RECONF2009-55 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2010/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reducing scheduling overheads in Dynamically Reconfigurable Processors |
| Sub Title (in English) | |
| Keyword(1) | Dynamically reconfigurable processors |
| Keyword(2) | dynamic scheduling |
| Keyword(3) | prefetch |
| Keyword(4) | hyperop |
| 1st Author's Name | Ratna Krishnamoorthy |
| 1st Author's Affiliation | Department of Electronics Engineering, the University of Tokyo() |
| 2nd Author's Name | Keshavan Varadarajan |
| 2nd Author's Affiliation | CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science |
| 3rd Author's Name | Mythri Alle |
| 3rd Author's Affiliation | CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science |
| 4th Author's Name | Ranjani Narayan |
| 4th Author's Affiliation | Morphing Machines Pvt. Ltd., Entrepreneurship Center, Indian Institute of Science |
| 5th Author's Name | Masahiro Fujita |
| 5th Author's Affiliation | VLSI Design and Education Center, the University of Tokyo |
| 6th Author's Name | S K Nandy |
| 6th Author's Affiliation | CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science |
| Date | 2010-01-26 |
| Paper # | VLD2009-70,CPSY2009-52,RECONF2009-55 |
| Volume (vol) | vol.109 |
| Number (no) | 393 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |