Presentation | 2009-12-04 FlexMerge : A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga TAKATA, Yusuke MATSUNAGA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper presents a novel logic optimization technique to minimize the number of LUTs for the post-processing of LUT-based FPGA technology mapping. The proposed method reduces the number of LUTs by merging two LUTs into an LUT using the don't care of each LUTs without changing the functionality. The experimental results show that the proposed method reduces about 4% LUTs of LUT networks for MCNC benchmark set while the existing method reduces about 2% LUTs of LUT networks. The run-time of the proposed method, however, is about 6 times longer than the existing method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | reconfigurable system / FPGA / logic synthesis / technology mapping |
Paper # | VLD2009-68,DC2009-55 |
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Committee | VLD |
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Conference Date | 2009/11/25(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | FlexMerge : A Logic Optimization Technique to Minimize Area for LUT-based FPGAs |
Sub Title (in English) | |
Keyword(1) | reconfigurable system |
Keyword(2) | FPGA |
Keyword(3) | logic synthesis |
Keyword(4) | technology mapping |
1st Author's Name | Taiga TAKATA |
1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
2nd Author's Name | Yusuke MATSUNAGA |
2nd Author's Affiliation | Faculty of Information Science and Electrical Engineering, Kyushu University |
Date | 2009-12-04 |
Paper # | VLD2009-68,DC2009-55 |
Volume (vol) | vol.109 |
Number (no) | 315 |
Page | pp.pp.- |
#Pages | 6 |
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