Presentation | 2009-12-04 Transistor-Array-Based OPAMP Layout and its Evaluation Arisa KAWAZOE, Toru FUJIMURA, Shigetoshi NAKATAKE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a novel MOS analog design style along with layout automation, called Transistor-Array (TA), which makes use of regular bulk structures. For typical OPAMP circuits, we laid out them in the custom layout style and the TA layout style, and compared the resultant with respect to the area. As well, we implemented the circuit into the TEG and measured their offset voltages to check the influences by the process variation. Analyzing these results, it is convinced that a design automation based on TA layout style is promsing to generate layouts with sufficient circuit quality as well as area utilization. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Transistor-Array / Analog Layout / OPAMP / Offset Voltage |
Paper # | VLD2009-60,DC2009-47 |
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Committee | VLD |
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Conference Date | 2009/11/25(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Transistor-Array-Based OPAMP Layout and its Evaluation |
Sub Title (in English) | |
Keyword(1) | Transistor-Array |
Keyword(2) | Analog Layout |
Keyword(3) | OPAMP |
Keyword(4) | Offset Voltage |
1st Author's Name | Arisa KAWAZOE |
1st Author's Affiliation | School of Environmental Engineering, The University of Kitakyusyu() |
2nd Author's Name | Toru FUJIMURA |
2nd Author's Affiliation | School of Environmental Engineering, The University of Kitakyusyu |
3rd Author's Name | Shigetoshi NAKATAKE |
3rd Author's Affiliation | School of Environmental Engineering, The University of Kitakyusyu |
Date | 2009-12-04 |
Paper # | VLD2009-60,DC2009-47 |
Volume (vol) | vol.109 |
Number (no) | 315 |
Page | pp.pp.- |
#Pages | 6 |
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