Presentation 2009-12-04
A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk
Masayuki KOBAYASHI, Wataru SENTO, Masahiko TOYONAGA, Michiaki MURAOKA,
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Abstract(in English) In this paper, a method which detects timing error points by using the logic simulation with back annotation of delay time variation by crosstalk is proposed. As an experiment, this method was applied to evaluate a multiplier and a CPU, and the result was that the rate of crosstalk points in the circuit was less than 40 %, and the rate of crosstalk points which generate timing errors was less than 10 %. This method reduces the correction points of wire by comparison to the conventional method, and will be able to accelerate the frequency of high performance circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Crosstalk / Logic Simulation / Circuit Design / EDA / CAD
Paper # VLD2009-58,DC2009-45
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Committee VLD
Conference Date 2009/11/25(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk
Sub Title (in English)
Keyword(1) Crosstalk
Keyword(2) Logic Simulation
Keyword(3) Circuit Design
Keyword(4) EDA
Keyword(5) CAD
1st Author's Name Masayuki KOBAYASHI
1st Author's Affiliation Information Science Division, Graduate School of Science, Kochi University()
2nd Author's Name Wataru SENTO
2nd Author's Affiliation Faculty of Science, Kochi University
3rd Author's Name Masahiko TOYONAGA
3rd Author's Affiliation Information Science Division, Graduate School of Science, Kochi University
4th Author's Name Michiaki MURAOKA
4th Author's Affiliation Information Science Division, Graduate School of Science, Kochi University
Date 2009-12-04
Paper # VLD2009-58,DC2009-45
Volume (vol) vol.109
Number (no) 315
Page pp.pp.-
#Pages 6
Date of Issue