| Presentation | 2009-12-03 An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism Tomohide NAGAI, Masashi IMAI, Takashi NANYA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the down scale of technology and the increase of transistor count, future processors are expected to be more susceptible to faults. In this paper, we propose a processor-level fault tolerance technique for chip multi-processors called "Pair & Swap" (P&S). We also propose a new metric called "Mean Computation To Failure" (MCTF) considering not only reliability but also performance. We evaluate the P&S and the traditional triple modular redundancy (TMR) by MCTF. The result shows that the MCTF of the P&S is about 1.5 times larger than that of the dynamic TMR. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Pair & Swap / graceful degradation / dependable chip multiprocessor / mean computation to failure |
| Paper # | VLD2009-51,DC2009-38 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism |
| Sub Title (in English) | |
| Keyword(1) | Pair & Swap |
| Keyword(2) | graceful degradation |
| Keyword(3) | dependable chip multiprocessor |
| Keyword(4) | mean computation to failure |
| 1st Author's Name | Tomohide NAGAI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo() |
| 2nd Author's Name | Masashi IMAI |
| 2nd Author's Affiliation | Komaba Open Laboratory, The University of Tokyo |
| 3rd Author's Name | Takashi NANYA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| Date | 2009-12-03 |
| Paper # | VLD2009-51,DC2009-38 |
| Volume (vol) | vol.109 |
| Number (no) | 315 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |