| Presentation | 2009-12-02 Simulation-Based Bus Width Optimization for Two-Level Caches Shinta WATANABE, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a simulation-based bus width and cache configuration optimization approach for two-level caches. First, we show that we can consider the cache hit/miss judgement and the bus width optimization independently. Second, the cache hit/mis judgments can be done effectively by applying our CRCB techniques. Then we show several properties for cache and bus width and propose an effective bus width optimization approach based on them. We have developed a system that optimizes cache and bus configuration where total memory access time or total energy consumption is minimized. Our proposed approach totally runs a maximum of 835.91 faster compared to the simple exhaustive approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cache memory / bus width / cache simulation / cache optimization / bus width optimization |
| Paper # | VLD2009-48,DC2009-35 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Simulation-Based Bus Width Optimization for Two-Level Caches |
| Sub Title (in English) | |
| Keyword(1) | cache memory |
| Keyword(2) | bus width |
| Keyword(3) | cache simulation |
| Keyword(4) | cache optimization |
| Keyword(5) | bus width optimization |
| 1st Author's Name | Shinta WATANABE |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2009-12-02 |
| Paper # | VLD2009-48,DC2009-35 |
| Volume (vol) | vol.109 |
| Number (no) | 315 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |