| Presentation | 2009-12-02 Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis Keisuke INOUE, Mineo KANEKO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In high-level synthesis of LSI, it is an important task to minimize the number of connections between modules (functional units and registers), and the number and sizes of multiplexers as well as the length of schedule, and the number of functional units and registers in terms of LSI chip area and operation performance. Recently, the authors have proposed an ILP description which executes simultaneously the three main tasks of high-level synthesis: scheduling, functional unit assignment, and register assignment. As an extension of this ILP description, this paper proposes an ILP-based treatment of connections between modules and multiplexers considering port assignment of functional units. The main contribution of this paper is to provide a general framework to minimize the number of connections, the number and sizes of multiplexers in cooperation with the adjustment of scheduling, functional unit assignment, register assignment, and port assignment of functional unit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-level synthesis / Port assignment / Multiplexer minimization / Integer Linear Programming (ILP) |
| Paper # | VLD2009-43,DC2009-30 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2009/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High-level synthesis |
| Keyword(2) | Port assignment |
| Keyword(3) | Multiplexer minimization |
| Keyword(4) | Integer Linear Programming (ILP) |
| 1st Author's Name | Keisuke INOUE |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST):Japan Society for the Promotion of Science (JSPS)() |
| 2nd Author's Name | Mineo KANEKO |
| 2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) |
| Date | 2009-12-02 |
| Paper # | VLD2009-43,DC2009-30 |
| Volume (vol) | vol.109 |
| Number (no) | 315 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |